Abstract
The difference between the threshold voltages (Vt) of PMOS and NMOS transistor is a critical issue in the operation of low voltage circuits. The P/N Vt balancing profit is analyzed in terms of sub-threshold leakage current, minimum supply voltage, and static noise margin. Balancing the P/N Vt reduces the lowest required supply voltage by 0.15-0.3 V. The use of our proposed Vt matching scheme enables CMOS LSI minimum supply voltage processing at 0.1 V.
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