Threshold voltage shift due to low energy electrons used in SEM voltage contrast testing

Abstract

Scanning electron microscope (SEM) voltage contrast testing is being developed for functional design verification, failure analysis, and development of VLSI devices. This technique imparts little electrical loading and requires no physical contact to the chip, both of which are advantages for device testing via internal nodes. One area of concern, however, is the effect of the low-energy electrons (<5 keV) on the transistor parameters. Even for incident electrons below 8 keV which do not penetrate to the gate oxide, a threshold shift has been observed in SOS MOSFET's. The parameter shift is a result of damage to the gate oxide by secondary X-rays generated by the electrons. Limits on the electron energy and fluence are set to minimize the threshold shift during SEM testing. It is found that under the proper conditions sufficient time is available to perform both voltage contrast imaging and nodal waveform measurements without incurring serious threshold voltage shifts.