Threshold voltage drift in phase change memories: scaling and modeling

Abstract

ABSTRACTThe phase-change-memory (PCM) relies on the ability of a chalcogenide material, usually Ge2Sb2Te5 (GST), to switch from the amorphous phase with a high electrical resistance (~MΩ) to a crystalline phase with a low electrical resistance (∼kΩ). The structural stability of the amorphous phase is critically affected by temperature-activated crystallization and resistance drift due to structural relaxation (SR) [1]. While amorphous chalcogenides are relatively stable with respect to crystallization, thanks to a high activation energy above 2 eV [2], the lower activation energy of SR can strongly affect the PCM electrical properties of the amorphous phase, including resistance, activation energy for conduction and, most importantly, the threshold voltage VT. The latter marks the boundary between read and programming operations in PCM, thus VT instability must be carefully predicted to minimize read disturbs within the array. To this purpose, understanding the switching mechanisms and modeling of VT is of utmost importance for PCM device development and scaling.