Threshold Switch Augmented STT MRAM: Design Space Analysis and Device-Circuit Co-Design

Abstract

We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70% larger sense margin, ~27% higher data stability with ~40% less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides $\sim 1.7\times $ larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ~10% less average power and demands only ~5% more write time extension than the STT MRAM to achieve the same level of variation tolerance.