Three-Level ZVS Active Clamping PWM for the DC–DC Buck Converter

Abstract

This paper presents the study of a dc-dc buck converter with three-level buck clamping (buck-buck), zero-voltage switching (ZVS), active clamping, and constant-frequency pulsewidth modulation (PWM). Other ZVS dc-dc converter topologies that employ three-level switching cells are introduced, and their steady-state dc gain is analyzed. This analysis shows that the buck-buck converter has characteristics that warrant a more detailed study. A feature that is common to all the introduced topologies is the theoretical reduction of the voltage stresses across the active semiconductors to 50% of the corresponding two-level converters. Accordingly, the switches of the buck-buck converter provide 50% of the blocking voltage of a ZVS two-level buck converter. The steady-state analysis of the converter is performed according to the description of the operation stages of the converter. Based on the performed analyses, a comparative discussion to other topologies is given. Furthermore, a topologic derivation of the circuit is presented, which provides ZVS operation to all semiconductors. Finally, a simplified design procedure is proposed, and used to design and build a prototype. Experimental results from a laboratory prototype are presented.