Three-dimensional PN junction capacitor for passive integration

Abstract

A wafer level three-dimensional (3D) PN junction capacitor for passive device integration on Si is developed. The 3D capacitor structure is created by deep trench etching of Si and appropriate doping. The salient characteristics of the PN junction capacitors fabricated in this study are as follows. The maximum areal capacitance density is 11.5 fF/μm2, the highest breakdown voltage is −20 V, and the minimum leakage current is 5 nA at an applied reverse voltage of −5 V. In comparison with the planar PN junction capacitor, the 3D junction capacitor can provide 8-12 times the capacitance density at the same doping concentration.