Three-Dimensional Networks-on-Chip: Performance Evaluation

Abstract

The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology for integrating a very high number of intellectual property (IP) blocks in a single die. The achievable performance benefit arising out of adopting NoCs is constrained by the performance limitation imposed by the metal wire, which is the physical realization of communication channels. With technology scaling, only depending on the material innovation will extend the lifetime of conventional interconnect systems a few technology generations. According to International Technology Roadmap for Semiconductors (ITRS) for the longer term, new interconnect paradigms are in need. The conventional two dimensional (2D) integrated circuit (IC) has limited floor-planning choices, and consequently it limits the performance enhancements arising out of NoC architectures. Three dimensional (3D) ICs are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, NoC is an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. This chapter quantifies the performance of 3D NoC architectures. It demonstrates functionality in terms of throughput, latency, energy dissipation, and wiring area overhead. It also addresses the temperature concerns that are apparent in 3D integrated circuits in general as well as many emerging 2D applications, showing that the characteristics of 3D NoCs limit what would otherwise be a dramatic increase in temperature, and in a certain case, even reduce temperature.