Three-wire cryoelectric memory systems

Abstract

Systems requirements dictate that a memory, capable of storing 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> - 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> bits, be bit or quasi-bit organized. Present-day techniques for controlling the geometric and material properties of a large, vacuum deposited, thin-film cryoelectric array are not sufficient to produce a 2-wire bit-organized memory with an acceptable operating margin. To circumvent this problem new systems, whose electrical operation is relatively independent of these variations, are needed. One such random access memory, the 3-wire cryoelectric memory system, is an example of this philosophy. The storage and selection functions are separated, the former being handled by an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</tex> line, while the latter is handled by an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Y</tex> line. For particular memory cell design, the system can be operated in a mode in which the selection current is independent of stored current. This eliminates one of the parameters responsible for variations in the threshold and disturb currents. An added feature of such a system is the uniformity in the stored current levels (in a properly designed cell), since the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</tex> line can be serially connected throughout all bits common to a particular digit. Although such a cell requires more structure than previously proposed cells, the operational advantages are judged to be the over-riding consideration.