Three-state log-aware buffer management scheme for flash-based consumer electronics

Abstract

Major digital consumer electronics such as smartphones and tablet PCs are equipped with flash memory because of its many advantages. However, its distinguishing characteristics, including erase-before-update, asymmetric read/write/erase cost and limited number of erase cycles, make it necessary to reconsider existing storage access designs in order to explore the hardware potential. For example, the buffer replacement scheme for flash-based systems should not only consider the cache hit ratio, but also the relatively heavy write and erase costs that are caused by flushing dirty pages. Most of the recent studies on buffer design focus on a clean-first LRU (Least Recently Used) strategy that evicts clean pages prior to dirty pages, in order to minimize the write access to flash. However, all of them failed to distinguish the cached pages that may have different effects on the flash device under various storage mangers. This paper proposes a three-state log-aware buffer management scheme, called TSLA, which considers not only the imbalance of read/write costs of flash memory but also the log block thrashing, associativity, and space utilization problems of log-based FTLs (flash translation layers). Experimental results show that the proposed solution is effective for reducing the garbage collection overhead under various FTLs, such as BAST, FAST and IPL.