Three stage low noise operational amplifier design for a 0.18 um CMOS process

Abstract

A new three stage low-noise, high-gain operational amplifier (Op-Amp) is proposed in this paper. Design strategies are discussed for minimizing noise and increasing gain. Multipath nested Miller compensation used for three stage operational amplifier. The circuit is designed in the 0.18μm CMOS technology. The HSPICE software was used for simulation. The simulation results show that the amplifier has a 128.5 dB open-loop DC gain and a unity gain-bandwidth of 794 MHz. Also input-referred noise of this circuit is 1.233 (nF/√Hz) at 1 MHz frequency.