Three-stage compression approach to reduce test data volume and testing time for IP cores in SOCs

Abstract

A three-stage compression technique that reduces test data volume and test application time for scan-based testing of intellectual property (IP) cores in system-on-chip integrated circuits is presented. In the first stage, referred to as width compression, the concept of scan chain compatibilities is combined with a method that exploits the logic dependencies between scan chains. This leads to a gated fanout decompression structure that uses c input channels to drive m scan chains (c≪m). Next, static compaction is used to reduce the number of test patterns, a step referred to as height compression. Finally, dictionary-based compression is used to further reduce test data volume. Structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. By combining the advantages of the gated fan-out structure and dictionary-based compression, the proposed approach significantly reduces the test data volume and testing time with very little hardware overhead for on-chip decompression. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits.