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Abstract
SUMMARYThree novel improved CMOS capacitance scaling schemes are presented and compared with some conventional schemes. The novel topologies that use a modified second‐generation current conveyor, an improved cascode current mirror and an OTA with two outputs connected in current steering configuration provide higher values of Q and better frequency responses than conventional structures using basic current mirror schemes, as the simple current mirror or cascode current mirrors. Simulation results and some measurements of a chip prototype are presented. Copyright © 2011 John Wiley & Sons, Ltd.
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