Three hardware implementations for the binary modular exponentiation: sequential, parallel and systolic

Abstract

Modular exponentiation is the cornerstone computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. We describe the characteristics of three architectures designed to implement modular exponentiation using the fast binary method: the first FPGA prototype has a sequential architecture, the second has a parallel architecture and the third has a systolic array-based architecture. We compare the three prototypes using the time/spl times/area classic factor. All three prototypes implement the modular multiplication using the popular Montgomery algorithm.