Thin-Film Transistor Simulations With the Voltage-In-Current Latency Insertion Method

Abstract

This article presents formulations for the voltage-in-current (VinC) latency insertion method (LIM) for thin-film transistors (TFTs). LIM is a fast circuit simulation algorithm that solves circuits in a leapfrog manner, without requiring intensive matrix operations present in SPICE-based simulators. This allows LIM to have a far superior scaling with respect to the size of the circuit resulting in significant time savings on large circuit networks. The VinC LIM formulation for the TFTs written in this article has the benefit of a better stability compared to the original LIM formulation which allows the use of larger time steps. The performance of the new algorithm is demonstrated through the simulation of numerical examples of large flat-panel display (FPD) circuits. It is seen that VinC LIM greatly outperforms basic LIM and commercial SPICE-based simulators, where the presented algorithm is able to simulate circuits with more than 10 million nodes or devices in a reasonable time, which is not viable in many modern day SPICE-based simulators.