Thin silicide development for fully-depleted SOI CMOS technology

Abstract

Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10/sup -7//spl Omega/-cm/sup 2/ is necessary for achieving low contact resistance in a sub-0.25-/spl mu/m fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed.