Abstract

For technology nodes beyond 14nm silicon nitride spacer etching has become a major challenge. Conventional plasma etching techniques based on CHF3/O2 cannot achieve thorough nitride removal on horizontal surfaces without inducing either CD loss or Si/SiGe source/drain recess. This leads to either gate leakage increase or poor raised source/drain epitaxy. To overcome atomic scale control issues faced with continuous plasma processes, several techniques aiming at achieving atomic layer etching or thin layer etching were recently described [1]. An original etching approach has been reported which consists in modifying the silicon nitride through H2 ion implantation by plasma (ICP or CCP) and then selectively removing the modified fraction of the layer thanks to chemical etching [2]. Layer modification depth is controlled thanks to plasma parameters (bias voltage and process time). This unconventional technique was demonstrated on 14nm FDSOI logic device and showed less than 1nm spacer CD loss, less than 0.6nm SiGe recess which enabled defect-free source/drain epitaxy [2]. Mechanisms for silicon nitride modifications and selective removal are discussed in this article by comparing downstream plasma, liquid-phase HF and gas-phase HF as removal techniques.

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