Thin Dielectric Spacer for the Monolithic Integration of Bulk Germanium or Germanium Quantum Wells With Silicon-on-Insulator Waveguides

Abstract

We propose an approach to monolithically integrate bulk germanium (Ge) or Ge quantum wells with silicon-on-insulator (SOI) waveguides through selective epitaxy and direct butt coupling. To prevent lateral epitaxial growth during the selective epitaxy, a dielectric insulating spacer layer is deposited on the sidewall facet of the SOI waveguide. With an SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> spacer that is 20 nm thick, the additional insertion loss penalty can be as low as 0.13 dB. We also propose and demonstrate a robust, reliable, and complementary metal-oxide-semiconductor (CMOS)-compatible fabrication process to realize sub-30-nm spacers.