Thermo-mechanical Reliability Study of High I/Os Flip Chip On Laminated Substrate Based on FEA, RSM and Interfacial Fracture Mechanics

Abstract

This paper described a comprehensive study of thermo-mechanical reliability of high input/outputs (I/Os) flip-chip on laminated substrate by using finite element analysis(FEA), response surface methodology(RSM) and interfacial fracture mechanics. Accelerated thermal cycling(ATC) tests for six specimens with different structures and materials were conducted firstly to determine the fatigue life and failure mechanism of the solder joints. Two-dimensional and Three-dimensional FEA corresponding to ATC tests were then conducted individually to analyze the mechanical behavior of the package under ATC conditions. Global-local FEA approach was used because of the large number of solder bumps and the complicated structure of the package. The simulation results of FEA accorded with the tests results well and a fatigue life model in related with accumulated strain energy density was built to estimate the solder joint fatigue life of the package. The combined effect of structural parameters including pad diameter, pad thickness, solder mask open, solder mask thickness and standoff height on the solder joint fatigue life were analyzed by the integration of two-dimensional FEA and central composite design (CCD) based RSM, and a response surface model was established to make the optimization. Due to imperfect manufacturing process, very small interfacial cracks commonly exist between the interface of solder joint and copper pad after reflow, the interfacial fracture behavior of the crack for different crack lengths under ATC conditions were investigated with two-dimensional FEA. Interfacial fracture mechanics and crack surface displacement extrapolation method were used to analyze the variations of strain energy release rate and phase angle at the crack tip