Thermal-Aware On-Chip Memory Architecture Exploration

Abstract

The memory architecture has the huge impact on the performance of embedded systems. Most of the current on-chip memory techniques focused on the optimization of timing performance, power consumption, and area. Thermal issue of memory subsystem has not been fully considered in these techniques. For on-chip memory architectures, the high temperature may cause the exponential increase of leakage, which becomes one of the major factors of power consumption. With the shrinkage of feature size and the great demand of silicon area, on-chip memory is the dominate contributor of the total leakage. Therefore, it is a challenging issue to manage the thermal cost of the on-chip memory architectures. In this paper, we focus on the optimization of the on-chip memory architecture that consists of cache and scratchpad memory (SPM). Our objective is to optimize the thermal behavior of the memory components for a target application with loops, while keeping the timing performance. We propose a thermal-aware memory architecture exploration algorithm TAME, and a thermal-aware data allocation algorithm TADA. These two algorithms collaborate to perform the memory architecture exploration, considering memory components' type, size, power, area and timing performance. Experimental results show that our method reduces the peak temperature of on-chip memory subsystem significantly, and at the same time the timing performance is even improved by making fully use of SPM.