Abstract
Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs in scaled devices are experimentally evaluated. In particular, SHEs of SOI devices with ultra-thin (UT) buried oxide (BOX) are measured using a four-terminal gate electrode. Then, the modeling of thermal resistance/conductance of interconnect wires are discussed. Finally, the co-optimization of thermal and electrical properties of devices in terms of analog performance is described.
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