Thermal treatment for preventing void formation on directly-bonded InP/Si interface

Abstract

The surface conditions of thin film InP epitaxial layers transferred to a Si substrate have been investigated in terms of void size, density, and area occupied by the voids, by changing the annealing temperature and ramping periods to reach the annealing temperature of 400 °C. Through a long ramp annealing time of 45 h, the voids generated were downsized by up to two orders of magnitude, and the total number of voids also greatly decreased compared that for the typical annealing process at 400 °C. This resulted in a reduction of the InP surface area occupied by voids from 3.96 to 0.03%. Then, successful fabrication of void-free 50 mm InP/Si substrates without forming any outgassing channels has been demonstrated.