Thermal-stress stability of yttrium oxide as a buffer layer of metal-ferroelectric-insulator-semiconductor field effect transistor

Abstract

The effect of thermal stress on the electrical properties of ferroelectric/semiconductor structure was investigated when introducing Y 2O 3 film as a barrier layer in the structure. Two different thermal stress states could be obtained by fast (400 °C/min) or slow (30 °C/min) cooling of sputter-deposited Y 2O 3 films on silicon wafer from 800 °C. The formation of interfacial layer containing Y–Si–O and SiO 2 layers while annealing could be characterized by using a spectroscopic ellipsometry. The introduction of strain-induced defects from thermal stress of the fast cooled sample showed a soft breakdown at low applying voltage. In the capacitance–voltage relation, a flat band voltage shift, hysteresis, and stretch-out phenomena were also observed. Nd 2Ti 2O 7 was spin deposited using sol-gel procedure on the Y 2O 3/Si to form a metal-ferroelectric-insulator field effect transistor structured sample. These Nd 2Ti 2O 7/Y 2O 3/Si samples were also furnace-annealed at 800 °C and cooled down to room temperature fast or slowly. One order lower value of leakage current, 1E−8 A/cm 2 was observed with these samples when comparing with the Y 2O 3/Si samples. A soft breakdown of the fast cooled sample seemed to have the same origin as the fast cooled Y 2O 3/Si sample, i.e., the strain-induced defects in the interfacial layer containing Y–Si–O and SiO 2 phases. Hysteretic gaps of the Nd 2Ti 2O 7/Y 2O 3/Si samples showed a possibility to be used as a memory window for ferroelectric gate.