Thermal Stress Reduction of Copper Through Silicon Via (TSV) with Annealing

Abstract

Electrodeposited copper is widely used in TSV filling due to its low resistivity. Unfortunately, its TEC of 17 × 10−6/°C causes thermal stress during annealing due to the mismatch with silicon TEC of 2 × 10−6/°C. In the upper region of the TSV, stress is released by the extrusion of copper when annealing. The results showed the extrusion height of copper TSV increases with the increase of temperature and the extrusion height is about 1.2 μm at 500°C for conventional copper TSV. Also, at via the bottom corner, this stress due to the mismatch in TEC between copper and silicon is accumulated. That stress is the reason for the cracks at the bottom corner of the conventional copper TSV. With our low TEC copper, the extrusion height of copper decreases to only 0.3 μm and no cracks occur at the via bottom corner. In addition, the resistivity values of low TEC copper are always lower than that of conventional copper in as electrodeposited copper and after annealing at different temperatures. The results suggest that the low TEC copper is not only good at reducing thermal stress in TSV due to annealing but also decreasing the resistivity of copper TSV.