Thermal Simulation Flow and Thermal Closure Methodology in High-Performance VLSI/SOC Design

Abstract

This paper describes our thermal simulation flow and thermal closure methodology based on one high-performance VLSI/SOC chip. Thermal simulation results help the design team to evaluate the cooling technology and verify the highest temperature on the chip. The developed flow is based on PowerDC tool from Cadence Design Systems to automate steps based on one configure file. We discuss more details about the tool, the configure file and power density file that are critical to the accuracy of simulation results. The general thermal closure methodology and engineering teams involved in the process are described in the paper with experimental results based on the high-performance SOC chip.