Thermal Performance Optimization of the Three-Dimensional Integrated Circuits Employing the Integrated Chip-Size Double-Layer or Multi-Layer Microchannels

Abstract

Abstract The chip-size integrated double-layer microchannels (DLMCs) and multilayer microchannels (MLMCs) are investigated to optimize the thermal performance of three-dimensional integrated circuits (3D ICs). The chip-size integrated DLMCs without a heat spreader and a heat sink reduce the hotspot temperature by almost 15 K for a nominal 3D IC structure. Meanwhile, the size is significantly smaller than the copper heat sinks, and the weight of the chip-size integrated DLMC is reduced by 99.9%. Furthermore, two chip-size integrated DLMCs lower the hotspot temperature by another 6.77 K compared with utilizing just one integrated DLMC on top of the chip structure. The results also show that the MLMCs have a great effect on reducing the hotspot temperature. We have established that the optimal layout is four layers. The hotspot temperature is reduced by 21 K and 102 times lighter in weight compared to nominal 3D IC structure. The proposed structure and results presented in this study pave the way for major innovations in resolving the thermal issues for the 3D ICs.