Thermal Modeling of Large Embedded GaN Transistors

Abstract

This paper highlights the recent thermal characterization and simulation work carried out on large area embedded GaN power transistors. Two types of embedded formats are characterized and compared. A package that has a bottom side thermal pad requires thermal vias is compared, at the system level, with a package that has a top side thermal pad that can be more directly interfaced to a heat sink. In both cases a thermal interface material (TIM) is used to provide electrical insulation. GaN power transistors have Ron·Qg Figure of Merit results that are more than 10 times better than SJ MOSFETS. However Ron increases substantially as the GaN channel temperature increases. Control of the channel temperature plays a major role in achieving the promised performance improvement expected from GaN devices. It is also vitally important that the heat removal strategies do not compromise the dynamic performance of these exceptional transistors.