Abstract

The analytic description of thermal stresses and strains in surface mount chip carrier assemblies have been studied by a nonlinear finite element method. Emphasis is placed on the effects of packaging material and package size on interconnection and package reliability. In parallel, test boards with 68-Pin plastic leaded chip carriers (PLCC) have also been made and subjected to temperature cycling. The observed failure mechanism of the solder joints agreed with the finite element results.

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