Thermal Evaluation of TSVs in 3D-Integration Technology

Abstract

3D technology promises significant benefits to offer shorter interconnect and higher integration systems enabling improved performance and lower power consumption. Nevertheless, 3D stacking is facing strong thermal challenges due to higher power density and minimal heat dissipation which might cause performance and reliability degradation. This paper discusses the thermal evaluation and modeling of 3D stacked ICs. A 3D computational fluid dynamics (CFD) thermal analysis tool called FloTHERM by Mentor Graphics is used to evaluate the effect of stacking the chips on the temperature rise of 3D ICs. In our thermal modeling, all stacked chips were treated as lumped blocks with estimated thermal conductivity of the TSV chip. The stacked chips have the same size (5x5x0.1mm). The power dissipated by each chip is 0.02 W and it was assumed that the power is uniformly distributed on each chip. The maximum junction temperature with number of stacked chips were also evaluated.