Abstract
CVD diamond substrates were: (a) plastic packaged as SOIC GaAs MESFET (chip and wire, flip chip) and PQFP GaAs PHEMT devices, and (b) as CuW-flanged ceramic packaged with Si LDMOS devices. The thermal performance milestones realized for the diamond-enhanced packages were: for GaAs/CVD diamond plastic packages, greater than 50% reductions in junction temperature at rated power, 20 W CW operation uninterrupted for 96 hours; for Si/CVD diamond CuW-flanged ceramic packages, a 65% reduction in junction temperature and a 44% reduction in maximum package temperature. These superior performance figures were achieved in part through the thermal engineering of the dominant thermal transport path from heat source to heat sink. The design, performance, and economic aspects of diamond insertion are discussed for high performance GaAs/CVD diamond and Si/CVD diamond electronic packages.
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