Thermal Coupling Among Channels and Its DC Modeling in Sub-7-nm Vertically Stacked Nanosheet Gate-All-Around Transistor

Abstract

In this article, the thermal coupling characteristic inside a vertically stacked nanosheet gate-all-around (NSGAA) transistor is investigated based on the calibrated TCAD simulation. It is found that an inhomogeneous temperature distribution exists among the channels of the transistor, due to the source/drain serial resistance and the self-heating effect. Temperature rising inside each channel can be characterized by thermal linear superposition of Joule Heat effect and thermal coupling effect. An extracting structure with replacing the silicon channel by insulator material based on the TCAD simulation is proposed to distinguish the above two components related to temperature for each channel. The calculation results show that the extracting method is well in agreement with the TCAD simulation. In addition, the impact of the space between two adjacent channels is also studied. Finally, based on the extracting procedure, an empirical thermal impendence matrix model and its iterative convergence calculation are established, considering the impact of Joule Heat, thermal coupling, and the impact of various spaces over a long range. The results show that the models and the iterative convergence calculation can well predict the temperature distribution inside the vertically stacked NSGAA transistor.