Thermal conductivity of Si nanowires with faulted stacking layers

Abstract

Faulted stacking layers are ubiquitously observed during the crystal growth of semiconducting nanowires (NWs). In this paper, we employ the reverse non-equilibrium molecular dynamics simulation to elucidate the effect of various faulted stacking layers on the thermal conductivity (TC) of silicon (Si) NWs. We find that the stacking faults can greatly reduce the TC of the Si NW. Among the different stacking faults that are parallel to the NW's axis, the 9R polytype structure, the intrinsic and extrinsic stacking faults (iSFs and eSFs) exert more pronounced effects in the reduction of TC than the twin boundary (TB). However, for the perpendicularly aligned faulted stacking layers, the eSFs and 9R polytype structures are observed to induce a larger reduction to the TC of the NW than the TB and iSFs. For all considered NWs, the TC does not show a strong relation with the increasing number of faulted stacking layers. Our studies suggest the possibility of tuning the thermal properties of Si NWs by altering the crystal structure via the different faulted stacking layers.