Thermal Challenges in 3D Stacks

Abstract

Thermal Management of high performance 3D SiP Modules is gaining momentum in telecommunication and networking applications. With increasing need for bandwidth and reduced real estate on boards, there is an acute need for 3D SiP modules. At the same time, the stacked modules come with a host of new challenges in terms of thermal management, packaging, thermo-mechanical stresses etc. This study looks at one such module with stacked dies for memories along with another high performance silicon all under a single lid. The study focuses on the effect of underfill materials on thermal performance, effect of through silicon vias, effect of non-uniform heat source on hot spots on the die etc. It will also focus on thermal management of a single module as well as a series of modules in a networking application. The effect of thermo-mechanical stresses will also be investigated and conclusions drawn on the effect of each of these parameters.