Thermal Aware 3-D Floorplanning on Multi-stacked Board of Smart Phone

Abstract

In this paper, we analyze the heat generation characteristics of components in a multi-stack PCB (Printed Circuit Board) structure of smart phone and find the optimized structure of components placement to minimize system temperature. The PCB in a smart device is conventionally composed of a single layer, so that components are placed on one side or both sides of single PCB. However, as the performance of components goes up, power consumption and the battery size have been gradually increased in order to maximize the running time. Accordingly, in order to increase the battery size in limited space of the smart phone, it is necessary to reduce PCB area on which the components are mounted. Recently, mobile phone makers are gradually adopting a new structure in which PCBs are stacked in multiple layers to increase mounting area. As a result, the heat generation phenomenon needs to be examined from a different viewpoint than the existing single layer PCB structure. In case of existing single-layer PCB, components can be contacted to heat spreader (heat pipe, bracket, metal or graphite sheet) through TIM. On the other hand, in case of multi-layer PCB configuration, components in between two boards have no direct contact with heat spreader and it makes chip temperature higher than before. We analyze chip temperature for different board placement of multi-stacked PCB in smart phone considering thermal performance. The location of high power components such as AP (Application Processor), RF, PMIC, CP (Communication Processor), and Flash Memory was a parameter. Finally, we can find optimal configuration that minimizes the max junction temperature for multiple power scenario.