Thermal- and Performance-Aware Address Mapping for the Multi-Channel Three-Dimensional DRAM Systems

Abstract

In this paper, we proposed thermal- and performance-aware address mapping (TPAMAP) for the multi-channel 3-D DRAM systems. TPAMAP reduces the thermal problem from the vertical stacking of the active banks in different DRAM channels and supports the mappings with the design tradeoffs of the temperature and performance. In our experiments, the peak temperature can be reduced by 1.1 °C ~ 12.3 °C for the 3-D DRAM system using TPAMAP. The cost function for the constraints of the temperature and performance is also proposed. In hardware design, we demonstrate the low-cost feature of TPAMAP in our hardware design.