Theoretical evaluation of a novel design for digital GaAs ICs

Abstract

The performance of a novel integrated logic (complementary level FET logic, CLFL) for digital GaAs ICs was investigated by circuit simulation. This novel circuit design is characterized by complementary levels and DFETs with very small negative V/sub TD/ values (V/sub TD/>or=-100 mV). The static power dissipation, the dynamic power dissipation, the propagation delay time, the dynamic logic swing, the noise margins, and the driving capability were calculated and compared with the corresponding quantities of the conventional E/D technology (DCFL). CLFL circuits are about 5-500 times less static-power-consuming than DCFL circuits at the same switching speed. Inverters with a propagation delay time of 20-100 ps have shown a minimum power-delay product of 0.1 fJ. Disadvantages are a higher number of devices (a factor of 1.2-2.1) and more extensive interconnections.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>