Abstract
This study attempts to investigate the warpage behavior of a flip chip package-on-package (FCPoP) assembly during fabrication process. A process simulation framework that integrates thermal and mechanical finite element analysis (FEA), effective modeling and ANSYS element death-birth technique is introduced for effectively predicting the process-induced warpage. The mechanical FEA takes into account the viscoelastic behavior and cure shrinkage of the epoxy molding compound. In order to enhance the computational and modeling efficiency and retain the prediction accuracy at the same time, this study proposes a novel effective approach that combines the trace mapping method, rule of mixture and FEA to estimate the effective orthotropic elastic properties of the coreless substrate and core interposer. The study begins with experimental measurement of the temperature-dependent elastic and viscoelastic properties of the components in the assembly, followed by the prediction of the effective elastic properties of the orthotropic interposer and substrate. The predicted effective results are compared against the results of the ROM/analytical estimate and the FEA-based effective approach. Moreover, the warpages obtained from the proposed process simulation framework are validated by the in-line measurement data, and good agreement is presented. Finally, key factors that may influence process-induced warpage are examined via parametric analysis.
Highlights
In recent years, there has been explosive and continuous growth in the consumer market for various smart products and Internet of Things (IoT) products, as well as the developing requirements of 5G communication, artificial intelligence (AI), and autonomous vehicles
In addition to high I/O quantity and miniaturization, further requirements of multi-functionality have aroused the development of the flip chip package-on-package (FCPoP) technology
This packaging technology has attracted a great deal of attention from the semiconductor packaging industry due to its compelling features including heterogeneous integration capability, high electrical performance, high bandwidth, low power consumption, small form factor, low cost, etc., leading to wide potential applications, such as high-performance application CPUs
Summary
There has been explosive and continuous growth in the consumer market for various smart products and Internet of Things (IoT) products, as well as the developing requirements of 5G communication, artificial intelligence (AI), and autonomous vehicles. I/O density, excellent electrical performance and miniaturization, and is commonly used in high-end smart chips in recent years. In addition to high I/O quantity and miniaturization, further requirements of multi-functionality have aroused the development of the flip chip package-on-package (FCPoP) technology. This packaging technology has attracted a great deal of attention from the semiconductor packaging industry due to its compelling features including heterogeneous integration capability, high electrical performance, high bandwidth, low power consumption, small form factor, low cost, etc., leading to wide potential applications, such as high-performance application CPUs. To date, research on FCPoP has been exceptionally limited. Hsieh et al [9] proposed a PoP technology with the flip chip structure for mobile device applications, which can be a bare die PoP packaging technology, a molded laser PoP packaging technology, or a silicon interposer substrate PoP technology to achieve thickness and warpage reduction
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
