The VLSI design of a two dimensional image processing array

Abstract

This paper presents the VLSI design of a two dimensional Image Processing Logic Array (IPLA). The IPLA consists of a two dimensional logic frame of nxn photodiodes, a set of decoders, a counter and some other useful components such as amplifiers gates etc. The IPLA enables whichever digital version of the image is to be created either by hardwired logic or under computer control; it can rapidly give one or more picture scan outputs (set of pels) simultaneously. Also, that array can immediately provide the total average intensity of the whole image or image part, that is an important factor in making quick decisions for the further processing such as regular decomposition, transformation, transmittion etc. The IPLA attempts to speed up the picture processes such as creation of hierarchical data structures, object detection and extraction, parallel, pipelined hierarchical orthogonal transformations etc., by scanning the logic array in various desired ways and providing the scanned pixels to the processor(s).