Abstract
This paper presents the VLSI architecture of a highly efficient configurable pre-processor supporting QR decomposition (QRD), sorted QRD (SQRD), and MMSE-SQRD for MIMO detections. The proposed design is architected based on the Givens Rotation algorithm and a high-throughput pipelined systolic array structure. Moreover, for achieving low-complexity, a novel norm-calculation scheme is utilized so that the overhead for the sorting operation is minimized. The circuit elements are also realized with the considerations of hardware sharing. The proposed pre-processor has been synthesized, placed, and routed using TSMC 90nm technology. The post-layout estimations show that this configurable pre-processor can support QRD, SQRD, and MMSE-SQRD, and can process 44M matrices per second for 4×4 MIMO systems with manageable complexity.
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