The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation

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On-board data handling sub-systems shall provide robust communication on-board spacecraft and have strict requirements in terms of reliability, fault-tolerance and redundancy. In the next years, on-board data handling sub-systems will be required to sustain high-speed payloads since satellites will host new high-resolution instruments, requiring a multi-gigabit data rate. The European Space Agency promotes the usage of a standard for the implementation of a very high-speed link for satellite on-board data-handling, SpaceFibre, that supports multi-lane communication links. Indeed, due to the stringent requirements of future on-board data handling subsystems, it will be necessary to have links that include more lanes to enhance system reliability and bandwidth. SpaceFibre aims at becoming the state-of-the-art for future on-board data handling subsystem, combining high-speed with high reliability and fault tolerance capability. In this paper, we introduce and report the development of an innovative multi-lane SpaceFibre core, and compares it with other promising space-oriented standards regarding multi-lane features. We present the results of a test campaign that aims at measuring SpaceFibre multi-lane performances in terms of recovery time after a lane failure, observing that the communication process can be completely restored between 4.42 μs and 6.30 μs. Implementation results on state-of-the-art space-oriented FPGAs, such as the Microsemi RTG4 and the Xilinx UltraScale Virtex KU060 are also included. Finally, we carry out a detailed power consumption analysis, including results for different core configurations, measuring the SpFi dynamic power consumption contribution to be between 576.7 mW and 148.4 mW for target configurations on a Microsemi RTG4.