Abstract

Concurrency is beginning to be accepted as a core knowledge area in the undergraduate CS curriculum—no longer isolated, for example, as a support mechanism in a module on operating systems or reserved as an advanced discipline for later study. Formal verification of system properties is often considered a difficult subject area, requiring significant mathematical knowledge and generally restricted to smaller systems employing sequential logic only. This paper presents materials, methods and experiences of teaching concurrency and verification as a unified subject, as early as possible in the curriculum, so that they become fundamental elements of our software engineering tool kit—to be used together every day as a matter of course. Concurrency and verification should live in symbiosis. Verification is essential for concurrent systems as testing becomes especially inadequate in the face of complex non-deterministic (and, therefore, hard to repeat) behaviours. Concurrency should simplify the expression of most scales and forms of computer system by reflecting the concurrency of the worlds in which they operate (and, therefore, have to model); simplified expression leads to simplified reasoning and, hence, verification. Our approach lets these skills be developed without requiring students to be trained in the underlying formal mathematics. Instead, we build on the work of those who have engineered that necessary mathematics into the concurrency models we use (CSP, {pi} -calculus), the model checker (FDR) that lets us explore and verify those systems, and the programming languages/libraries (occam-{pi}, Go, JCSP, ProcessJ) that let us design and build efficient executable systems within these models. This paper introduces a workflow methodology for the development and verification of concurrent systems; it also presents and reflects on two open-ended case studies, using this workflow, developed at the authors’ two universities. Concerns analysed include safety (don’t do bad things), liveness (do good things) and low probability deadlock (that testing fails to discover). The necessary technical background is given to make this paper self-contained and its work simple to reproduce and extend.

Highlights

  • Concurrency and formal verification, if they are taught at all at undergraduate level, are taught as distinct subjects

  • We focus on the model of concurrency known as Process Oriented Design [Wel00], [WP10], [Wel13a], which is based on the formal process algebras of Hoare’s Communicating Sequential Processes (CSP) [Hoa[85], Ros[97], Ros10] and Milner’s π -calculus [Mil99]

  • Behaviour examined includes the initial orderings of signals to/from the device, what happens when its internal components starts looping, deadlock and livelock freedom, and operational safety (“do no bad”) and liveness (“do good”)

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Summary

Introduction

Concurrency and formal verification, if they are taught at all at undergraduate level, are taught as distinct subjects. The novelty in what we offer in this paper is a way to teach both together in such as way that they reinforce each other and enable deeper understanding and application If these are taught early in the curriculum, they become second nature and provide a stronger foundation for education in computer engineering. At Kent, concurrency has been a course module at the undergraduate level since 1986 It has taken place during the second year. Teaching them in a combined way, as discussed in this paper, commenced in 2010 in the second year Students at this stage were familiar only with object-oriented programming through Java and with only a modest mathematical foundation. At UNLV concurrency and verification has been taught together as one part of a graduate course (for students already holding a B.Sc. or equivalent in computer science), which has been offered three times

Concurrency is essential
The need for verification
Research led teaching: our experiences
Paper organization
On-line resources
Concurrency and verification methodology
Process orientation
Processes
Synchronising channels
Synchronising barriers
Networks
Design by pictures and composition
Formal verification
Primitive processes
Channels
Barriers
Conditions
Case study: robot control system
The device
Executable model
Informal analysis of the initial behaviour of Device
Formal model
Formal analysis
Initial event sequences
Assertions in CSPM
Case study: mutually assured destruction
The problem
Tracking down the deadlock
Why did soak-testing not find the deadlock?
Revised model
Revised formal model
Revised executable model
Reflection
On the robot control system
On mutually assured destruction
Testing and verification
An alternative solution to the deadlock
Cost of the verified fix and further wins
Final thoughts
A CSP model of the twin processes
Correcting the behaviour of the twin processes
Full Text
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