The SURF algorithm on a FPGA-based platform

Abstract

The SURF algorithm is suitable for being implemented on small computation platforms for its advantages of scale-invariant, rotation-invariant, and low computation burden. This paper focuses on the realization of the SURF algorithm upon a small FPGA-based platform for objects recognition in real-time. By following the hardware and software co-design concept the entire system is implemented and embedded in the FPGA of a SoPC. The hardware part of the system includes image processing circuits and peripheral circuits. The image processing circuits include RGB to gray transformation circuit and image integral circuit. Peripheral circuits include Laplacian of Gaussian filters circuit and NiosII process circuit. In software part, it includes SURF related operations such as: interest point descriptor, interest point matching, and the software for the system control. It has experimentally been proven that the resulting system satisfies the design goals of objects recognition, rotation-invariant, and scale-invariant. But, in the resulting system, there are only several modules realized in hardware because of the hardware resource limitation of the FPGA chip, causing the recognition speed cannot have very much improvement.