Abstract
The ceaseless drive to produce cheaper and better products has compelled the Semiconductor Industry to continue to innovate. Because of its priority that chips or dies of different techniques can be integrated in a package, SIP (System In Package) is applied more and more widely in the embedded control system. At the same time, the test of SIP has also been a big challenge owing to the amount constraint of the pads while so many functions are integrated in. A new testing scenario by DSU, JTAG and LEON2 processor for a SIP micro-computer is presented and a testing system including Chip test, PCB test and Post-packaging is designed for the SIP micro-computer test. The testing scenario and test system make the product engineers' task easier by improving the testability of SIP.
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