The Steady-State DC Gain Loss Model, Efficiency Model, and the Design Guidelines for High-Power, High-Gain, Low-Input Voltage DC–DC Converter

Abstract

The phase modulated full bridge resonant transition converter (PMRTC) is commonly used for high-gain, high-power applications, as PMRTC converters retain the qualitative nature of hard switched pulse-width modulation counterparts with additional damping ( $R_d$ ), where $R_d$ is load, transformer turns ratio and frequency dependent. The PMRTC converter enables operation at a higher switching frequency due to the soft-switching nature, thereby achieving better power density. For battery fed high-power, high-gain applications, PMRTC exhibits a significant drop in the dc gain due to $R_d$ and other nonidealities, limiting the maximum frequency of operation. Thus, computing this drop and analyzing the effects of switching frequency becomes necessary in achieving the required steady-state dc gain. From the analysis, it is observed that, for a choice of switching frequency above $f_{s\;{\rm critical}}$ , the required steady-state dc gain is not achieved for any turns ratio. Hence, to increase the switching frequency of operation of a PMRTC converter, a two-transformer configuration is adapted and with this configuration, the dc gain loss model, power loss, and efficiency model and small-signal model are established. The design guidelines on the choice of switching frequency and transformer turns ratio based on the proposed models is described. The proposed models with the presented design guidelines are validated in simulations and hardware prototype for a 1 kW PMRTC converter.