The status and trend of novel process and technology in nano-IC manufacturing

Abstract

The technology development of micro-nano electronics in global IC industry is summarized and reviewed in the present paper. There are many challenges and opportunities as the innovative devices and materials have gradually been applied to IC manufacture. As ITRS 2011 Roadmap shows that gate length will shrink to 20 nm in 2013, the industry mainstream manufacturing technologies of the nano-electronics seems moving toward the goal. It is well known that the IC technology development basically depends on material science. In Section 2, some new material and process technologies are highlighted, such as strained silicon, high K and metal gate, ultra-low K, 450 mm silicon wafer, and immersion lithography technologies are the foundation of IC manufacture. The process integration for advanced CMOS manufacture technology is discussed in Section 3. As an example, 20 nm process flow scheme is explained and some comparison is made to the precious generation technology. The main process flow difference between 28 nm technology and 20 nm technology is illustrated and some explanations are presented. In Section 4, 3D system packaging technology is introduced. Some preliminary TSV experimental data made by SMIC are shown. It is expected that 3D TSV Wide I/O would eventually be inevitable in 28 nm production and beyond. In Section 5, the research and development of nonvolatile memory are summarized, such as RRAM, PcRAM and MRAM. Some lab experimental and measurement results from SMIC are demonstrated. It is believed that PcRAM, which is relatively mature technology, mass production will probably come up in the mainland in a few years. In Section 6, a couple of new transistor architectures are introduced and some experimental data are demonstrated, such as local SOI and GAA, and some experimental data are shown. Finally, the comments for domestic R&D strategy in IC area are proposed to future IC R&D direction.