Abstract

In the past decade, fundamental graphene research has indicated several excellent electronic properties for graphene such as ultrahigh carrier mobility (~200,000 cm2 / Vs), micrometer - scale mean free path, electron - hole symmetry and quantum Hall effect [ 1 - 6 ] . Such extraordinary properties , unmatched by any other conventional thin film material, make it an extremely promising material for next generation nano - integrated devices. Despite of this, several fundamental challenges still lay ahead before the introduction of graphene in nanodevices can be envisaged. One major challenge is the ability to confirm the outstanding reported properties for graphene grown over large - area s , on to appropriate substrates . Since graphene was isolated first time in 2004 [ 7 ] , several techniques have been demonstrated to produce high quality graphene. The most common techniques are micromechanical exfoliation of single crystal graphite [ 7 ] , chemical vapor deposition (CVD) growth on transition metals and dielectric insulators [ 8 - 10 ] , chemical reduction of graphite oxide (GO) [ 11 ] , carbon nanotubes (CNTs) unzipping [ 12 ] , and high temperature thermal decomposition of silicon carbide (SiC) [ 13 ] . Among these methods, the highest performance graphene devices have been fabricated using mechanically exfoliated flakes. Carrier mobility in excess of ~200,000 cm2 / V s has been reported for suspended single layer exfoliated graphene at room temperature [ 6 , 14 ] . CVD growth is widely used to produce large - area (up to 30 inch) , high quality graphene on transition metal substrates [ 8 , 15 ] . However, the graphene layers produced in the ways described above need invariably to be transfer red onto a semiconducting or insulating subs trate for device fabrication. Unfortunately, for several compelling reasons, this transfer approach is not compatible with the commercial fabrication of actual nanodevices. First, the transfer of flakes tends to affect the quality of the graphene layer in terms of contamination and formation of detrimental folds and ripples, which can ultimately degrade the performance of the electronic devices [ 16 , 17 ] ...

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