The semiconductor - dielectric interface from PN junction periphery and its influence on reliability of power devices at high temperature

Abstract

Data sheets of commercial power semiconductor devices and modules available at this time on the market indicate a maximum permissible junction temperature specified in a range of 125 -200degC. Operation above the specified value is not possible without risk of device failure, although this is desirable in emerging power electronics applications. Typical device blocking electrical characteristics at high junction temperature are presented and analyzed. A portion of blocking current-voltage characteristic given by a PN junction at reverse bias voltage can be fitted to linear variation. At higher applied voltage towards the breakdown region deviation from linear variation is exhibited. By increasing the junction temperature from 150degC towards 200degC and above this value, the portion of the current-voltage characteristic exhibiting linear variation becomes more reduced. If the applied voltage reaches the portion of electrical characteristic with deviation from linear variation towards the breakdown region, thermal instability of the characteristic is developed in short time. Device failure is possible if the applied voltage is not suppressed. Analysis of failed devices operated in such conditions indicates excessive high current or even electrical short-circuit for PN junctions at reverse applied voltage. It is shown that such behavior is due to a spot of material degradation located at the junction periphery. Most of leakage current flow in a thin interfacial layer between the semiconductor material and the passivating dielectric material from the junction edge accounts for many device failures during operation at high temperature.