The safe operating volume as a general measure for the operating limits of LDMOS transistors

A Ferrara,R J E Hueting,J Schmitz,P G Steeneken,L Van Dijk,M Swanenberg,A J Scholten,A Heringa,B K Boksteen

doi:10.1109/iedm.2013.6724577

Abstract

The operating limits of a transistor are conventionally determined by characterization of the curves that form the boundary of the safe operating area (SOA) in the two-dimensional drain current-voltage Q d , V ds ) plane [1, 2]. The shape of these SOA curves depends on parameters such as pulse time t pulse , ambient temperature T amb and area of the transistor A [3, 4]. Consequently, this way of characterizing the safe operating limits does not result in a single safe operating range for the transistor, but in many different curves that depend on operating conditions and transistor geometry. Besides the drain-source voltage Vd s and the gate-width W gate normalized drain current I dn (I dn - Id/W gate ), the junction temperature T j also plays an essential role in determining the safe operating limits of a transistor with a certain cross-section. Therefore, it is proposed to extend the SOA concept by adding a temperature T j -axis. In this way, the safe operating range can be represented by a volume in the three dimensional (ld n , V ds , T j ) space, which we define as the safe operating volume (SOV). In this work, extensive measurements of the safe operating limits of SOI LDMOS transistors are presented. Integrated temperature sensors are used to measure the junction temperature of the devices up to the edge of the operating range. By comparing measured SOV data for varying t pulse , T amb and A for devices of identical cross-section (Figs. 2-5) it is demonstrated that the SOV is nearly independent of operating conditions and device area. This establishes the SOV as a general measure for the safe operating limits of transistors. The usefulness of the SOV concept is demonstrated by showing how conventional two-dimensional SOA curves for different operating conditions and device areas can be predicted once the SOV and the effective thermal impedance Z th, eff of the LDMOS transistor have been determined (Table I and Figs. 6-7).

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