The role of adaptation and resiliency in computation and power management: Special session paper

Abstract

Variations, both static and dynamic in nature, impact the performance and power-efficiency of microprocessors and other digital integrated circuits. While static process variations can often be mitigated through binning or by post-silicon tuning, dynamic variations change as a function of time and environment and cannot be reduced by static tuning. Examples of these types of dynamic variations include power supply (V CC ) droop, temperature change, and device aging over time. The droop magnitude, frequency and duration depend on the complex interaction of capacitive and inductive parasitics at the board, package, and die levels and change with the workload and current demand [1-3]. V CC droops contain high-frequency (i.e., fast changing) and low-frequency (i.e., slow changing) components and occur locally and/or globally across the die. Temperature variations occur at a relatively slower time scale with local hot spots on the die, depending on environmental and workload conditions as well as the heat-removal capability of the package. Further, transistor aging slowly degrades the drive current over time as a function of gate bias and temperature conditions. Conventional designs build in V CC guardband (V CC GB) at a target frequency to ensure correct functionality even in the presence of worst-case dynamic variations. In the digital core, this GB accounts for the delay increase on critical paths when dynamic variations occur and guarantees that timing constraints are met even under worst-case conditions. In the storage arrays (register files and caches) this GB is added to the static minimum operating voltage (V MIN ) to obtain the resultant operating V MIN and results in an increase of both leakage and dynamic array power. The key design aspect of adaptive and resilient designs is to remove a part of this GB, such that logic timing and memory functionality can be met at a lower V CC . This improves energy efficiency and improves battery life; a key consideration in mobile and handheld platforms. The mitigation of the design GB can be achieved in two fundamentally different ways. For dynamic variations with time scales in the order of hundreds of μs to ms (such as temperature variations or transistor aging), a reactive scheme where any functional error is avoided is applicable. For example, embedded temperature sensors can be used to trigger changes in the clock frequency or changes in the supply voltage, such that at low temperatures (when transistor currents are higher) a faster clock (at iso-VCC) or a lower supply (at iso-clock frequency) can be employed [4]. For dynamic changes which occur in time scales of ns to μs, such reactive schemes are impossible by design. Hence, an alternative scheme can be employed where timing errors (in logic) or read-write errors (in memory) are allowed to happen. Once errors occur, they are detected, and the errant instruction is replayed with proper care such that data integrity is maintained. A combination of such adaptive schemes (Fig. 1) result in the mitigation of a major part of the design GB, resulting in higher energy efficiency.