The Research of Efficient Dual-Port SRAM Data Exchange without Waiting with FIFO-Based Cache

Abstract

This paper proposes a program of efficient dual-port SRAM data exchange without waiting with FIFO-based cache, which is targeted for timely, massive and interactive features of data transmission in MIMO systems, using FIFO as a dual-port SRAM external cache to achieve real-time data exchange between multiple systems or processors. The program can solve time conflict and data covering problem in the competitive state of data storage, reduce the transmission delay to wait for data exchange. This paper uses dual-port SRAM CY7C019 to do a simulation test for the program, which can realize effective addressing between memory and CPU in address mapping way. By the analyses to the system performance, the effectiveness and feasibility of this program is proved.