The Research and Efficient FPGA Implementation of Ghash Core for GMAC

Abstract

GMAC (Galois Message Authentication Code) is a special case of authenticated encryption mode GCM (Galois/Counter Mode) when it acts as a stand-alone MAC. As the hash function of GMAC, Ghash is based on the GF (2 128 ) multiplier. It is the algebraic properties of Ghash that support incremental authentication of GMAC. In this paper, an efficient hardware implementation on Xilinx Virtex 5 FPGA platform, in terms of performance, of Ghash core is presented. The proposed hardware implementation has been thoroughly tested using commercial simulation tools ModelSim and its functionality has been verified. The synthesis results show that this efficient implementation of Ghash core does not introduce extra design complexity and has high throughput, which is up to 15.382 Gbps, and it can meet the requirement of GMAC for high-speed and highly efficient authentication.